1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device built in a discrete device or an IC (Integrated Circuit).
2. Description of the Background Art
FIG. 7 is a cross section schematically showing the configuration of a semiconductor device of a first conventional technique. Referring to FIG. 7, a DMOS (Double diffused Metal Oxide Semiconductor) transistor is formed in a semiconductor substrate. This DMOS transistor has, mainly, an nxe2x88x92 layer 101, an n+ layer 102, a p-type diffusion region 103, an n+ diffusion region 105, a gate insulating layer 112, and a gate electrode layer 106.
nxe2x88x92 layer 101 is formed deeply from a first main surface of the semiconductor substrate toward a second main surface side. p-type diffusion region 103 is formed so as to be in contact with nxe2x88x92 layer 101 in the first main surface. In the first main surface in p-type diffusion region 103, n+ diffusion region 105 is formed so as to be adjacent to p+ diffusion region 104.
Gate electrode layer 106 is formed on the first main surface so as to face p-type diffusion region 103 sandwiched between nxe2x88x92 layer 101 and n+ diffusion region 105 via gate insulating layer 112. An insulating layer 113 is formed so as to cover gate electrode layer 106, and a source electrode 108 is formed so as to be connected to n+ diffusion region 105 and p+ diffusion region 104 which are exposed from insulating layer 113.
On the second main surface side of p-type diffusion region 103, nxe2x88x92xe2x88x92 layer 107 is formed so as to be in contact with nxe2x88x92 layer 101. nxe2x88x92xe2x88x92 layer 107 has impurity concentration lower than that of nxe2x88x92 layer 101. n+ layer 102 is formed on the second main surface side of nxe2x88x92 layer 101 and nxe2x88x92xe2x88x92 layer 107, and a drain electrode 109 is formed so as to be connected to n+ layer 102.
In the first conventional technique, as shown in FIG. 8, nxe2x88x92 layer 101 is formed so that its cross-sectional area in the lateral direction of the drawing is decreased from the source electrode side (first main surface side) toward the drain electrode side (second main surface side). nxe2x88x92xe2x88x92 layer 107 is formed so that its cross-sectional area in the lateral direction of the drawing increases by the same amount.
In the structure, when each of the source and gate is set to 0V and a positive bias is applied to the drain, the DMOS transistor enters a withstand checking state. At this time, a depletion layer extends, as shown by a dotted line in FIG. 8, in the entire area of nxe2x88x92 layer 101 and nxe2x88x92xe2x88x92 layer 107 and a part of each of p-type diffusion are 103 and n+ layer 102 which are in contact with nxe2x88x92 layer 101 and nxe2x88x92xe2x88x92 layer 107.
Assuming now that the cross-sectional area in the lateral direction of the drawing of nxe2x88x92 layer 101 decreases with an exp curve (exponential function curve), the concentration in nxe2x88x92xe2x88x92 layer 107 is sufficiently low, and the electric line of force hardly enters nxe2x88x92xe2x88x92 layer 107 side and that the electric field is uniform in the cross section in the lateral direction of the drawing of nxe2x88x92 layer 101, the electric field in the cross section in a position (x) is derived by the following equation 1.
E(x)=(q/xcex5)xc2x7{aN(exp(bx)xe2x88x921)/b+M}/{a(exp(bx))}xe2x80x83xe2x80x83(Equation 1)
In the equation 1, q denotes an electronic charge, N indicates impurity concentration of nxe2x88x92 layer 101, xcex5 indicates a dielectric constant of silicon (Si), and M represents the number of space charges in n+ layer 102. The position (x) denotes a distance between the junction of nxe2x88x92 layer 101 and n+ layer 102 and the source side.
When the relation of M=aN/b (equation 2) is satisfied in the equation 1, the equation 1 is expressed by the following equation 3.
E(x)=qN/(xcex5b)xe2x80x83xe2x80x83(equation 3)
By the equation 3, the electric field E(x) in the cross section in the lateral direction of FIG. 8 becomes always constant irrespective of the position (x). In the normal structure (structure in which there is no nxe2x88x92xe2x88x92 layer 107 in FIG. 7 but nxe2x88x92 layer 101 is formed on the entire face), a step junction is formed. Consequently, the electric field decreases monotonously with distance from the source side toward the drain side. In contrast, in the structure shown in FIG. 7, a constant electric field can be obtained, so that nxe2x88x92 layer 101 can be made thinner than that in the normal structure. As a result, by a trade-off between a withstand voltage and ON-state resistance (effective on-state resistance), the technique can exceed the limit of the normal structure.
In the first conventional technique, the cross-sectional area in the lateral direction of the drawing of nxe2x88x92 layer 101 decreases with distance from the source side toward the drain side. Consequently, there is a structural optimum value in the relation with the resistance in nxe2x88x92 layer 101. The resistance in the direction from the source side toward the drain side in the first conventional technique is obtained by the following equation 4. Specific resistance of nxe2x88x92 layer 101 is similar to xcex1/N.
R=xcex1/Nxc2x7∫1/axc2x7exp(xe2x88x92bx)dx=xcex1/Nabxc2x7(1xe2x88x92exp(xe2x88x92bl))xe2x80x83xe2x80x83(equation 4)
xcex1 in the equation 4 denotes a factor of proportionality of the specific resistance and impurity concentration. In the equation 4, to reduce the resistance, it is optimum that there is no nxe2x88x92xe2x88x92 layer 107 on the source side and nxe2x88x92layer 101 is formed in the entire surface. Consequently, effective ON-state resistance RS becomes the minimum in the following equation.
RS=Rxc2x7axc2x7exp(bl)=xcex1/(Nb)xc2x7(exp(bl)xe2x88x921)
From the equation 3, N/b is a constant. When N/b is set as xcex2, the effective ON-state resistance RS is expressed as the following equation 5.
RS=xcex1xc2x7xcex2/(Nxc2x7N)xc2x7(exp(Nl/xcex2)xe2x88x921)xe2x80x83xe2x80x83(equation 5)
Since the function becomes the minimum when Nl/xcex2≈1.6, the optimum impurity concentration N which minimizes the effective ON-state resistance RS exists, and the result b is also determined. Therefore, the optimum value exists in the entire structure.
A second conventional technique will be described as another technique.
FIG. 9 is a cross section schematically showing the configuration of a semiconductor device in the second conventional technique. Referring to FIG. 9, in the second conventional technique, in place of nxe2x88x92xe2x88x92 layer 107 shown in FIG. 7, a pxe2x88x92 layer 110 is formed. The pn junction between pxe2x88x92 layer 110 and nxe2x88x92 layer 101 extends almost in the direction perpendicular to the first and second main surfaces of the semiconductor substrate (thickness direction). The impurity concentration of pxe2x88x92 layer 110 and that of nxe2x88x92 layer 101 are controlled to be the same, thereby obtaining the same effect as that of the first conventional technique.
Since the configuration other than the above is substantially the same as that of the above-described first conventional technique, the same components are designated by the same reference numerals and their description will not be repeated.
In the second conventional technique, by providing pxe2x88x92 layer 110, the electric line of force from the space charge of nxe2x88x92 layer 101 enters pxe2x88x92 layer 110 side at a predetermined rate. Consequently, as the electric line of force extends from the drain side toward the source side, it extends from the inside of nxe2x88x92 layer 101 and gradually enters pxe2x88x92 layer 110 side, so that the electric field in nxe2x88x92 layer 101 is maintained to be constant. By the effect, the electric field of nxe2x88x92 layer 101 becomes almost uniform except for an area around p-type diffusion region 103 and n+ layer 102, so that an effect similar to that of the first conventional technique can be obtained.
As a result, to prevent an increase in density of electric line of force in both of the configurations of the first and second conventional techniques, the shape of nxe2x88x92 layer 101 is controlled so that, in the first conventional technique, the electric line of force always extends. In the second conventional technique, pxe2x88x92 layer 110 of the opposite conduction type for terminating the electric line of force is disposed.
Further, the second conventional technique is characterized in that the performance can be improved by making the pattern in the lateral direction of the drawing finer for the following reason. Even if the pattern in the lateral direction is reduced to the half of the whole in the configuration of the second conventional technique, when the space charge is the same value, a similar operation can be performed. By doubling the impurity concentration of nxe2x88x92 layer 101, an operation can be performed in a manner similar to that before the pattern is made finer. Since the cross-sectional area in the lateral direction of the drawing of nxe2x88x92 layer 101 in the device area is reduced at a predetermined rate, simply, the resistance can be reduced to the half by the same withstand voltage. As described above, the second conventional technique has an advantage such that the improved effective ON-state resistance can be obtained by making the pattern finer.
The structures of the first and second conventional techniques have, however, the following problems.
The configuration of the first conventional technique has a problem such that, it is difficult to accurately control the structure in which the cross-sectional area in the lateral direction of the drawing of nxe2x88x92 layer 101 decreases with distance from the source side toward the drain side and, in a normal process, an actual effect is smaller with respect to the performance theoretically expected.
The configuration of the second conventional technique has a problem such that means which largely increases the process cost is required such as multiple epitaxial growth to balance the concentration in nxe2x88x92 layer 101 and the concentration in pxe2x88x92 layer 110 and to form the pn junction between nxe2x88x92 layer 101 and pxe2x88x92 layer 110 perpendicularly to the first and second main surfaces and deeply to a certain extent and, further, it is difficult to control the means.
Although the second conventional technique has the advantage such that the effective ON-state resistance can be improved by narrowing the pattern in the lateral direction of the drawing as described above, it also has a problem such that the formation of the finer pattern in the lateral direction of the drawing requires a more difficult process.
An object of the invention is to provide a semiconductor device which can be easily formed while suppressing increase in process cost and has an improved trade-off (effective ON-state resistance) between a withstand voltage and ON-state resistance by generating an electric field almost uniform in the direction perpendicular to the surface of a semiconductor substrate.
A semiconductor device of the invention has a silicon substrate of a first conduction type, an insulated gate type field effect transistor, and a dielectric layer. The silicon substrate has first and second main surfaces facing each other. In the insulated gate type field effect transistor, a main current flows between the first main surface and the second main surface. The insulated gate type field effect transistor has: a first impurity region of a second conduction type formed in the first main surface; a second impurity region of the first conduction type formed in the first impurity region; a gate electrode layer facing the first impurity region sandwiched between a first conduction type region in the silicon substrate and the second impurity region via a gate insulating layer; and a dielectric layer formed in the silicon substrate so as to be adjacent to the first conduction type region in the silicon substrate and made of a material having a dielectric constant higher than that of silicon.
In the semiconductor device according to the invention, the dielectric layer having a dielectric constant higher than that of silicon is formed so as to be adjacent to the first conduction type region in the silicon substrate. Consequently, in a withstand voltage device state, an electric line of force generated in the silicon substrate gradually enters the dielectric layer from the first conduction type region with distance from the drain side toward the source side. It can make the electric field almost uniform in the depth direction of the substrate in the first conduction type region. Thus, the thickness of the first conduction type region can be reduced and, as a result, the trade-off between the withstand voltage and on-state resistance (effective on-state resistance) can be improved.
It is sufficient to form the dielectric layer so as to be adjacent to the first conduction type region. Unlike the first conventional technique, it is unnecessary to change the cross-sectional area in the depth direction of the substrate. Unlike the second conventional technique, it is unnecessary to control the impurity concentrations of the regions of opposite conduction types neighboring to each other to the same. Consequently, the device can be easily fabricated and an increase in process cost can be suppressed.
When the space charge in the first conduction type region is the same, even when the pattern is reduced in the direction of the first and second main surfaces of the substrate (lateral direction), an effect similar to the above can be obtained. Concretely, even when the pattern is reduced to the half in the lateral direction, when the impurity concentration of the first conduction type region is doubled and the same space charge as that before the pattern is reduced is set, an operation similar to that before reduction of the pattern can be performed. Therefore, while improving an trade-off between the withstand voltage and the on-state resistance, the size of the device can be reduced.
In the semiconductor device, preferably, the dielectric layer is constructed so that the dielectric constant decreases with distance from the first main surface side toward the second main surface side.
With the configuration, the dielectric layer can be controlled so that the distribution opposite to the distribution of the electric field in the first conduction type region in the withstand voltage device state can be set, so that the charge can be generated uniformly.
In the semiconductor device, preferably, the dielectric layer is formed on the second main surface side immediately below the gate electrode layer.
With the configuration, occurrence of resistance of a junction type field effect transistor can be prevented, so that the on-state resistance can be further improved and the fabrication is also facilitated.
Preferably, the semiconductor device is further provided with a region of the second conduction type formed between the dielectric layer and the first conduction type region in the silicon substrate.
With the configuration, an effect of terminating the electric line of force by depleting the second conduction type region in the withstand voltage device state is produced. Even when the dielectric constant of the dielectric layer is set to be low, an improved trade-off between the withstand voltage and the on-state resistance can be achieved.
In the semiconductor device, preferably, the dielectric layer becomes wider and the first conduction type region in the silicon substrate becomes narrower with distance from the first main surface side toward the second main principal side.
Thus, an effect of extending the depletion layer toward the first conduction type region side is obtained in a manner similar to the first conventional technique. Even when the dielectric constant of the dielectric layer is set to be low, an improved trade-off between the withstand voltage and the on-state resistance can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.